The present invention relates generally to a method of fabricating dielectrically isolated regions, and more specifically to an improved method of fabricating back diffused bonded oxide substrates having dielectrically isolated islands.
Devices in integrated circuits are formed by introducing impurities into a surface of a substrate. This requires the use of a plurality of masks to form regions of different depths and impurity concentrations. Acceptability of the finally formed devices depends upon alignment of the diffused regions. Thus, there is a great emphasis on schemes to align a mask to a substrate to assure proper alignment of the diffused regions. For junction isolated substrates, the first diffusion is from a top or front surface and consequently, all the diffusions may be aligned relative to the first diffusion. This technique may include positioning an indicia on a substrate and performing the first and subsequent diffusions using an indicia on the mask to align with the indicia on the substrate.
For devices formed in dielectrically isolated islands of the type described in U.S. Pat. No. 3,865,649 to Beasom, the dielectrically isolated islands are formed from a first surface which subsequently becomes a buried surface and the devices are formed therein by diffusion into a second surface opposite the first surface which does not exist in the initial material. Thus, no initial mark may be formed which allows alignment of the diffused device regions to the dielectric isolation. Since it is unacceptable in some applications for diffused regions of the device to touch the dielectric isolation, more care and time have to be used to align the mask relative to the dielectric isolation. Since the islands have inwardly sloping sides, the surface area available for forming the diffused regions is a function of the amount of starting material removed. Thus, the size of the islands as perceived from the surface varies considerably. At present, the diffusions are aligned to the outside of the islands. In view of the variation in the size, the alignment in a possibly increased island will not assure alignment in the remaining islands on the wafer. The varied island size also results in a varying alignment tolerance. This causes difficulty in judging alignment visually.
To solve these problems, a support material rectangular indicia is formed during the formation of the dielectric isolation of starting material islands in one of the dielectrically isolated islands as described in U.S. Pat. No. 4,309,812 to Hull. The resulting indicia appears on the front processing face during the thinning of the substrate to produce the dielectrically isolated islands. An X indicia on a mask is positioned over the four corners of the rectangular indicia to align the mask and substrate for subsequent processing. The rectangular indicia is not used for any back side processing, only front side processing since it is formed with the isolation moats.
In addition to the dielectric isolation, wherein the lateral and bottom walls are formed simultaneously, there has been a substantial growth in semiconductor-on-insulator (SOI) wafer fabrication. A thin substrate is separated from a handle wafer by an insulator layer. These structures may be formed by high dose oxygen implantation (SIMOX), bonded wafers, ZMR or full isolation by porous oxidation silicon (FIPOS) These processes generally do not include backside processing, and any buried layers are produced by epitaxial deposition of the resulting substrate over the buried layer regions.
Any backside processing generallY results in uneven surfaces which are very undesirable for bonding since the valleys result in unbonded regions. These unbonded regions fall out when front side isolation dielectric trenches are formed. Presently, uneven oxide surfaces are used as alignment indicia in backside processing.
Thus, it is an object of the present invention to provide a method of fabricating a semiconductor-on-insulator integrated circuit capable of backside processing.
Another object of the present invention is to provide a semiconductor-on-insulator integrated circuit with backside processing and improved alignment.
These and other objects are achieved by forming an alignment moat of a first depth on a first surface of a substrate and performing all backside processing using the alignment moat, forming a first oxide layer on the first surface and bonding it to a handle wafer by oxide bonding. The substrate is then thinned from a second surface opposite the first surface down to a thickness less than the depth of the alignment moat so the alignment moat is exposed at a third surface. Isolation, either dielectric or junction, is then formed in the third surface extending down through the substrate to the first oxide layer. Topside processing is then conducted. While anisotropic chemical etching is used to form the alignment moat so as to provide a depth indicator, the dielectric isolation trenches are formed by reactive ion etching.
The backside processing includes diffusing impurities having an opposite conductivity type than that of the substrate to a depth at least equal to the depth of the alignment moat. Impurities to form a buried region, which are the same conductivity type as the substrate, are formed to a depth substantially less than the alignment moat depth. If a non-oxide mask is used as the last masking step in the backside processing, an additional oxide layer may be formed prior to bonding. If an oxide mask is used as the last mask in the backside processing, it must be stripped and a fresh layer of oxide must be applied to the first or back surface prior to bonding.